1. What is the logic synthesis? What are its main steps with Design Compiler?
  2. What are Design Compiler/PrimeTime objects?
  3. How to describe environmental attributes of a design?
  4. What are design rule constraints? How to make them more conservative?
  5. What are design constraints?
  6. What are group and ungroup? How to use them to change logic partition in a design?
  7. What is structuring? How to enable Design Compiler's structuring optimization?
  8. What is flattening? How to enable Design Compiler's flattening optimization?
  9. What is Static Timing Analysis (STA)?
  10. What is a timing arc, a start point, an end point, a path delay, and a timing path?
  11. What are the steps of STA, and top-down STA flow when using Synopsys PrimeTime
  12. How many types of STA? what are they?
  13. How to constraint the internal timing paths between registers in a design with one clock?
  14. How to constraint the internal timing paths between registers in a design with multiple synchronous clocks?
  15. How to constraint the internal timing paths between registers in a design with asynchronous clocks?
  16. How to specify an input delay with set_input_delay?
  17. How to specify an output delay with set_output_delay?
  18. What is a false path, How to set a false path using PrimeTime?
  19. How to read a Design Compiler/PrimeTime timing report?