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  1. How to implement a XOR gate using a 2:1 multiplexer (MUX)?
  2. How to implement a 2-bit magnitude comparator with 4:1 multiplexer?
  3. How to find the maximum frequency a circuit can work?
  4. How to design a one-shot circuit?
  5. Detect a pattern 0110 in a serial bit stream: data. A 0 cannot be used in more than one sequence. When the pattern found, output F is 1, otherwise it is 0. Draw its state diagram, and write its RTL code in Verilog.
  6. When a signal crosses from one clock domain to another, what should do to reduce the occurrence of metastability?
  7. An FIFO which clocks data in at 100 mhz and clocks data out at 80mhz. On the input there is only 80 data in any order during each 100 clocks. In other words, a 100 input clock will carry only 80 data and the other twenty clocks carry no data (data is scattered in any order). How big the FIFO needs to be to avoid data over/under-run. (We got this question from a co-worker, and we do not know where he got it. If you are its author, you can contact us at admin@www.asichowto.com.)
  8. There is a UNIX file called A, which has several copies scattered in different directories. If we want to delete them all, what should we do?
  9. How to implement a 1-bit full adder with 2 to 1 multiplexers?
  10. How to implement a 1-bit full subtract or with 2 to 1 multiplexers?
  11. How to detect more than one 1s in the last 3 samples of a bit stream?