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  1. How to define a macro with directive `define?
  2. How to share Verilog code with directive `include?
  3. How to define a constant with parameter and localparam?
  4. How to specify time unit and precision?
  5. How to generate a waveform?
  6. How to generate a clock?
  7. What accounts a rising transition -- posedge?
  8. What accounts a falling transition -- negedge?
  9. How to model combinational logic?
  10. When do we have to use a label in a procedure construct?
  11. What's difference between conditional operator and if statement?
  12. How to use generate for loop to instantiate a module?
  13. How to instantiate a module?
  14. How to change a parameter of a module?
  15. How to model a D latch?
  16. How to avoid unintended D latches?
  17. How to model a D flip-flop with an asynchronous reset?
  18. How to model a D flip-flop with a synchronous reset?
  19. How to model inertial delay?
  20. How to model transport delay?
  21. How to use model a pipeline or shift registers?
  22. How to avoid race conditions?
  23. How to generate random numbers?
  24. How to read data from a file with $readmemb and $readmemh?
  25. How to write data to a file with $display and its variants?
  26. How to define a task? and how to enable (call) it?
  27. How to define a function? and how to enable (call) it?
  28. How to model a tristate?
  29. How to model a bi-directional port?
  30. How to model a decoder?
  31. How to model a seven-segment decoder?
  32. How to model an encoder?
  33. How to model a priority encoder?
  34. How to model a Barrel shifter?
  35. How to model a multiplexer?
  36. How to generate a parity?
  37. How to model a comparator?
  38. How to design an adder with an assign statement?
  39. How to design an adder with an always block?
  40. How to design a ripple carry adder with a generate for loop?
  41. How to design a carry-lookahead adder with generate for loops?
  42. How to design a carry-select adder with generate for loops?
  43. How to model multipliers?
  44. How to design a clock divider by an even, odd, or fraction number?
  45. How to model a up counter with an asynchronous reset?
  46. How to model a down counter with an asynchronous reset?
  47. How to model a counter with an asynchronous reset, a load, a count enable, and an output enable signals?
  48. How to detect 101 sequence based on a Moore finite state machine (FSM)?
  49. How to detect 101 sequence using a Mealy finite state machine (FSM)?
  50. How to model a ROM?